Integrated circuit inductor structure and non-destructive etch depth measurement

ABSTRACT

A method for forming an electrical device structure in an integrated circuit comprises providing a substrate; forming a passivation layer thereon; forming a plurality of through holes in the passivation layer, the through holes; removing substrate material under the passivation layer by means of isotropic etching, thus forming at least a first cavity in the substrate beneath the plurality of through holes; forming a dielectric layer on top of the passivation layer to plug the through holes, thereby creating a membrane; and creating an electrical device, such as e.g. an inductor, above the membrane.

TECHNICAL FIELD

[0001] The present invention generally relates to IC-technology and morespecifically the invention relates to the formation of an electricaldevice structures such as e.g. an inductor structure, particularly aspiral inductor structure for radio frequency (RF) applications,integrated in an integrated circuit (IC), to the electrical devicestructure and the integrated circuit themselves, and to a method ofetching and measuring etched depth non-destructively.

TECHNICAL BACKGROUND

[0002] The Problem Area and Known Solutions

[0003] Advanced silicon bipolar, CMOS or BiCMOS circuits are used todayfor high-speed applications in the 1-5 GHz frequency range, replacingcircuits previously only possible to realize using III-V basedtechnologies.

[0004] Inductor elements are often needed in high-frequency circuitsbuilding blocks like resonators and filters. An object common to allintegrated technologies is to obtain inductors with high qualityfactors, so-called Q-values, and high operating frequencies (limited bythe resonance frequency f_(R), at which Q has fallen to zero).

[0005] Recent advances in silicon IC processing technology have allowedinductor layouts with higher inductance per area and lower lossesbecause of reduction of feature sizes and multilayer metallization withthick oxide to isolate the inductor from the substrate. A typicalintegrated inductor for 1-2 GHz circuits has inductance values in the1-10 nH range and will occupy an area up to 500μm ×500μm, which make itvery large and costly to integrate. There are still considerable lossesbecause of the resistivity of the metallization, coupling to thesubstrate and losses in the substrate. Inductors elements in the 1-10 nHrange with Q-values higher than 15 at 1-2 GHz are hard to obtain usingsilicon IC-technology.

[0006] Integrated inductors are usually designed as octagonal or squarespirals metal stripes 1 on an oxide 2 formed above a semiconductorsubstrate 3 as illustrated in FIG. 1. An equivalent circuit for suchinductor structure is schematically shown in FIG. 2. The Q-value can becalculated at low frequency (where the substrate parasitic capacitancesyet do not dominate the performance) as Q=ωL/r (ω=2πf, f being thefrequency; and L and r are the inductance and the resistance,respectively, of the inductor).

[0007] Because of the capacitance C_(ox) of the isolation materialbetween the metallization pattern and the substrate, and the siliconsubstrate's conducting properties, i.e. its capacitance C_(si) andresistance R_(si), see FIG. 2, the Q-value is reduced in the frequencyrange of interest (ranging from say a couple of hundred MHz to 10 GHz).

[0008] By using the upper conductor levels in a multilayer metallizationsystem to design the inductor, the capacitance C_(ox) is decreasedbecause the inductor is further displaced from the substrate groundplane by a thick oxide. The Q-value of the inductor is consequentlyincreased.

[0009] Another, more drastic, method is to selectively remove most of orall silicon under the inductor, see e.g. U.S. Pat. No. 5,539,241 (Abidiet al.); U.S. Pat No. 5,930,637 (Chuang et al.), U.S. Pat. No. 5,773,870(Su et al.); and U.S. Pat. No. 5,384,274 (Kanehachi et al.) . The C_(ox)parameter is lowered by the additional distance to the substrate createdby the hole. This results in higher Q-values and higher self-resonantfrequencies. The Q-value can be increased by a factor of two by such aremoval in the form of a silicon etch from the backside of thesubstrate, giving air gaps of several hundred micrometers, but suchtechniques are not regarded as feasible in large scale production ofsilicon IC.

[0010] Solutions combining increased oxide thickness and partialsubstrate removal are known. In U.S. Pat. No. 5,833,299 (Merill et al.)is described a method where V or pyramidal shaped grooves are etched inthe substrate, filled with oxide and planarized to form local islandswith the result of a considerably increased isolation oxide thickness,compared to the rest of the circuit. On top of these islands, integratedinductors are formed.

[0011] Other methods to reduces the losses from the silicon substrateare disclosed in e.g. U.S. Pat. No. 5,742,091 (Hé bert), where patternsof deep trenches filled with isolation material (already available inhigh-performance RF-IC process flows), are placed under the inductorstructure to reduce the losses.

[0012] Improved techniques to remove silicon from substrate includeformation of cavities in the substrate. In EP 0 971 412 A2 (Yoshida), amethod is disclosed where large cavities (100 μm wide) are formed in thesubstrate, and subsequently filled with e.g. oxide, whereafter aninductor structure is formed thereon, and the material used to fill thecavity is then removed in a final step, to create an air-filled hole inthe substrate.

[0013] In U.S. Pat. No. 6,025,261 (Farrar et al.), an inductor structureis described which incorporates polymer filled cavity structures etchedin the passivation layer situated under the metal pattern for theinductor and the semiconducting substrate. However, the cavity structureis only formed in the passivation layer on top of the silicon substrate,and because of the limited thickness of this layer and the lower ∈_(r),compared to substrate silicon, the effectiveness of this structure isprobably very limited.

[0014] In microelectromechnical technology (MEM), device structures areneeded that can be used as sensors for pressure, acceleration,temperature etc. These structure can also be integrated on a chip, wheredetection electronics can be placed. In U.S. Pat. No. 6,012,336 (Eatonet al.) is disclosed a capacitance sensor structure which includesremoving part of the silicon substrate, filling it with an insulator(such as silicon dioxide), and forming a structure on top of it, servingas the sensor.

[0015] Problems with Known Solutions

[0016] A solution is needed where silicon is removed under an integratedinductor structure. It must be compatible with conventional silicon ICprocessing, and add a minimum of additional process steps to theexisting flow. The method must also be able to remove silicon fully orpartly over areas larger than 500 μm ×500 μm, since this isapproximately the size of an integrated inductor used in communicationequipment at 1-2 GHz of operating frequency.

[0017] Previously described concepts, referred to as prior art, includeprocessing which is complex and complicated or not compatible withconventional IC processing or do involve an excessive number of steps.

[0018] Other known methods include filling the etched cavity withisolating material, e.g. silicon dioxide or a polymer. The dielectricconstant ∈_(r) of these materials are indeed lower, i.e. better, thanthat of silicon. However, an empty cavity has the lowest dielectricconstant (i.e. ∈_(r)=1), so if no filling can be used, this will bepreferred.

[0019] Yet other methods do not provide for structures including emptycavities, which are strong enough to withstand subsequent processing,i.e. formation of a multilayer metallization system, which is part ofthe subsequent conventional IC flow. This may be particularly relevantfor larger inductor structures such as 500 μm ×500 μm, and larger.

SUMMARY OF THE INVENTION

[0020] It is consequently an object of the present invention to providea method in the fabrication of an integrated circuit, particularly anintegrated circuit for radio frequency applications, for forming anelectrical device structure, particularly an inductor structure, whileovercoming at least some of the problems associated with the prior art.

[0021] It is a further object of the present invention to provide astructure formation method, which is capable of fabricating inductorstructures, which obtain high Q-values and high resonance frequency.

[0022] It is still a further object of the invention to provide suchstructure formation method, which is capable of fabricating electricaldevice structures, including inductor structures, which are mechanicallystrong and durable.

[0023] It is yet a further object of the invention to provide suchstructure formation method, which is simple to perform, and which iscompatible with conventional processing techniques.

[0024] It is in this respect a particular object of the invention toprovide such method that adds a minimum of additional process steps to aconventional IC process.

[0025] These objects among others are, according to one aspect of theinvention, fulfilled by a method comprising the following steps:

[0026] providing a semiconductor substrate;

[0027] forming a passivation layer above the substrate;

[0028] forming a plurality of through holes in the passivation layer;

[0029] removing semiconductor substrate material under the passivationlayer by means of isotropic etching using the passivation layer providedwith through holes as hardmask, thus forming a first cavity in thesemiconductor substrate substantially underneath the through holes;

[0030] forming a dielectric layer on top of the passivation layer toplug the through holes, thereby creating a membrane above the cavities;and

[0031] creating an electrical device, such as e.g. an inductor, abovethe membrane.

[0032] Preferably, the method includes that the plurality of throughholes formed in the passivation layer are dividable into a first and asecond sub-group, respectively, such that adjacent through holes withina sub-group are more closely located than adjacent through holesbelonging to different sub-groups; that semiconductor substrate materialunder the passivation layer is removed to form also a second cavity inthe semiconductor substrate substantially underneath the through holes,such that the cavities are separated by a portion of semiconductorsubstrate material, which supports the membrane above the cavity.

[0033] Furthermore it is an object of the present invention to providean electrical device structure, particularly an inductor structure,resulting from above said fabrication method; and an integrated circuitcomprising such a structure.

[0034] According to a second aspect of the present invention there isthus provided an electrical device structure, particularly an inductorstructure for radio frequency applications, comprising:

[0035] a semiconductor substrate;

[0036] a dielectric layer structure thereon;

[0037] an electrical device on top of the dielectric layer structure;and

[0038] a cavity structure in the semiconductor substrate, where theupper boundary of the cavity structure is defined by the dielectriclayer structure, and where the cavity structure has a lateral extensioncomparable to that of the electrical device, and is arranged underneaththe electrical device to decrease the electrical coupling between theelectrical device and the substrate.

[0039] The cavity structure comprises at least one air-filled space; andthe dielectric layer structure includes a plurality of through holes,said through holes being plugged by dielectric material.

[0040] In a preferred version, the cavity structure comprises aplurality of air-filled spaces and at least one portion of semiconductorsubstrate material extending to the dielectric layer structure forsupporting the dielectric layer structure mechanically, where theportion of semiconductor substrate material separates at least two ofthe plurality of air-filled spaces.

[0041] According to a third aspect of the present invention there isprovided an integrated circuit, particularly an integrated circuit forradio frequency applications, which comprises the electrical devicestructure according to the second aspect of the invention.

[0042] The residual silicon substrate support provides for amechanically strong structure, where still a silicon removalarea-utilization factor of more than 90% is obtained, i.e. more than 90%of the silicon substrate material beneath the inductor is removed andreplaced by air, which has a very low dielectric constant. Thus, thequality factor and self-resonance frequency of the inductor areconsiderably improved.

[0043] Further, there is an object of the present invention to provide amethod of etching and measuring etched depth non-destructively.

[0044] According to a fourth aspect of the present invention there isthus provided a method of etching and measuring etched depthnon-destructively, comprising the steps of:

[0045] providing a semiconductor substrate;

[0046] forming a dielectric layer above the substrate;

[0047] forming a plurality of through holes in the dielectric layer;

[0048] removing semiconductor substrate material under the dielectriclayer by means of isotropic etching using the dielectric layer providedwith through holes as hardmask, thus forming a cavity in thesemiconductor substrate;

[0049] providing the ratio between the etch rate of the isotropicetching in the semiconductor substrate material in a horizontal and in avertical direction, respectively;

[0050] optically and non-destructively measuring the horizontal distancefrom an outermost one of the through holes to an edge of the cavitythrough the dielectric layer; and

[0051] estimating the etched depth, i.e. the etched distance in thevertical direction, from the provided etch ratio and the measuredhorizontal distance.

[0052] Further advantages and characteristics of the present inventionwill be disclosed in the following detailed description of embodiments.

BRIEF DESCRIPTION OF DRAWINGS

[0053] The present invention will become more fully understood from thedetailed description of embodiments of the present invention givenhereinbelow and the accompanying FIGS. 1-6, which are given by way ofillustration only, and thus are not limitative of the invention.

[0054]FIG. 1 is a plan top view (to the left), and a cross-sectionalview (to the right), respectively, of a typical integrated inductordesign comprising a spiral inductor arranged above a conductingsubstrate.

[0055]FIG. 2 is an equivalent circuit for the integrated inductor ofFIG. 1.

[0056]FIGS. 3a-e are highly enlarged cross-sectional views of a portionof a semiconductor structure at various steps of processing according tothe present invention. FIG. 3a illustrates a starting structure, i.e. asilicon substrate upon which a passivation layer is formed; FIG. 3billustrates the structure subsequent to etching of holes; FIG. 3cillustrates the structure subsequent to isotropic cavity etching; FIG.3d illustrates the structure with the holes being plugged; and FIG. 3eillustrates the finished structure.

[0057] FIGS. 4-6 are SEM images of cross-sections of a semiconductorstructure resulting from processing according to the present invention.FIGS. 4 and 5 show the structure in two different enlargementssubsequent to cavity etching and FIG. 6 shows the structure portion ofFIG. 4 subsequent to hole plugging.

[0058]FIGS. 7a-d are schematic top plan views of different cavityformation designs according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0059] In the following description, for purposes of explanation and notlimitation, specific details are set fourth, such as particularprocesses, techniques, etc. in order to provide a thorough understandingof the present invention. However, it will be apparent to one skilled inthe art that the present invention may be practiced in other embodimentsthat depart from these specific details. In other instances, detaileddescriptions of well-known processes, methods, and techniques areomitted so as not to obscure the description of the present inventionwith unnecessary details.

[0060] With reference to the drawings an inventive embodiment of an ICfabrication process sequence, which includes formation of an inductorand of an empty cavity beneath the inductor, is described in detail.

[0061] The process can be fully integrated in different fabricationflows for integrated circuits, e.g. CMOS or bipolar or BiCMOS technologyfor RF-IC:s, with only minor modifications of the details describedbelow.

[0062] The process follows initially a typical conventional process flowvia formation of device isolation and active areas in a siliconsubstrate 11, formation of active devices etc., up to the point wherethe metallization (back-end) begins (not illustrated). The inductorstructure could be located either on top of an area intended for adevice (the illustrated case) or on top of an isolation area.

[0063] Next, a passivation layer 13, separating the metal from theactive devices, consisting of ˜2 μm of low-temperature oxide (PETEOS) isdeposited on the silicon substrate, the result of which beingillustrated in FIG. 3a. This is an integral part of a typical processsequence for the metallization, but will here also be used as a hardmaskfor silicon etching, since a conventional photoresist mask is lesslikely to withstand the silicon etch applied later in the flow. In thecase the inductor is to be located on top of an isolation area a furtherlayer of oxide (not illustrated) is existing between substrate 11 andpassivation layer 13. If a planarization step is needed in the processflow, it may be performed at this stage.

[0064] Photoresist is deposited and patterned by lithography (notillustrated). The pattern consists of an array of holes or contactholes. The holes may be equally spaced in an x*y matrix configuration,but other geometries, such as patterns with circular/radial geometry mayalso be applied. The size of the contact holes should be kept atminimum, since that will make it easier to plug the holes at a laterstep. The distance between the holes is not critical, but if spaced toomuch apart, this will results in a non-uniform bottom surface of thecavity to be formed. This will be discussed later in the text.

[0065] Holes 15 through oxide down to the silicon surface are dry-etchedusing conventional etch tools, e.g. RIE (reactive ion etching) usingCF₄/CHF₃ chemistry. After etching, the resist is removed and the waferis cleaned from any etch residues using standard process steps. Theresulting structure is shown in FIG. 3b. In the matrix of holes aresidual grid-like layer 17 of oxide is thus obtained.

[0066] Next, a cavity 19 is formed in the substrate by isotropic siliconetch using well-known dry-etching techniques (e.g. SF₆ or NF₃chemistry), the result of which being illustrated in FIG. 3c. Theetching depth is not very critical, but the more silicon that can beremoved, the larger is the improvement of the inductor structure. Theisotropic etch will at the same time create a side-etch 21, in the sameorder as the depth, which will broaden the structure.

[0067] An experimental design, with a 100×100 μm hole mask (0.45 μmholes, 0.9 μm spaced, oriented as an x*y matrix), using a 20-25 μm deepsilicon etch, shows that it is possible to create a cavity ofapproximately 130 μm ×130 μm which can withstand further processingwithout collapsing the structure, or loss of planarity. A scanningelectron microscope (SEM) photo of the cross section of the resultingstructure is shown in FIG. 4.

[0068] When the distance between the holes is increased, the bottom ofthe cavity will become less even, and the mean effect depth of thecavity will slowly decrease. In the experimental design, the hole pitch(i.e. the sum of the hole diameter and the spaced apart distance) isaround {fraction (1/15 )} the depth of the cavity; hence an almostsmooth surface at the bottom of the cavity is obtained.

[0069] The silicon etch will also slowly etch the hardmask. After 20-25μm of silicon etching in SF₆, around 1 μm of the hardmask remained.However, it is important that the erosion is limited to the top, so thatthe hole dimension is not widened and so the hole size can be kept undercontrol.

[0070] Since a typical integrated inductor for 1-2 GHz circuits haveinductance values in the 1-10 nH range and occupies areas up to or above500 μm ×500 μm, a plurality of 100 μm×100 μm hole matrixes spaced apartapproximately 35 μm can be fabricated to cover such areas. In the caseof a 500 μm×500 μm inductor sixteen hole matrixes are arranged in a 4×4matrix, which, after isotropic etching, results in a 4×4 matrix ofcavities.

[0071] The area between the respective cavities will not be fullyremoved, hence a supporting string 20 of 10-15 μm wide silicon will beleft between the cavities. In this way, arrays of cavities can becreated, with a silicon removal area-utilization factor of more than90%, while still a mechanically strong structure is obtained. Thesupporting string can also be divided into supporting pillars, tofurther increase the utilization factor, by properly spaced holes, seefurther the discussion with reference to FIGS. 7a-d. In the SEM image ofFIG. 5 two cavities 19 separated by a support 20 are shown.

[0072] The processing continues by depositing 1.5 μm of oxide 23 on topof the structure, with the purpose to seal the holes and thus create amembrane 24 over the air-filled cavity 19, as shown in FIG. 3d. Theoxide may consist of a three-layer structure. The oxide thickness ispreferably selected such that the total oxide thickness, including theremaining thickness of the hardmask, is similar to the device-to-metalisolation thickness as used in a typical conventional process flow.Actually, in this case, around 1 μm is possible to use to seal the holeand create the membrane 24. Also, the holes can be made smaller, e.g.0.25 μm instead of the used 0.45 μm, if necessary, which will furtherreduce the requirements on the minimum deposited oxide thickness.

[0073] The hole size is selected small (0.45 μm diameter) so that usinga reasonable oxide thickness, it is possible to completely plug theholes with oxide, without oxide being deposited into the cavity. In FIG.6, the structure of FIG. 4 is shown after this oxide deposition step.The cavity is completely sealed with no oxide in it.

[0074] Processing then continues with formation of a multi-layermetallization arrangement 25 to create an integrated inductor 27. Notethat only a portion of such integrated inductor 27 above a single one ofa plurality of cavities are illustrated in FIG. 3e. It shall beappreciated that a plurality of cavities are formed beneath the completelateral extensions of inductor 27. For the formation of inductor 27 atleast two metallization layers 29, 31 and a passivation layer 33 inbetween, in which a via hole contact 35 is formed, are needed.

[0075] With reference now to FIGS. 7a-d some different cavity formationdesigns will briefly be discussed. The dots outside the cavitystructures indicate merely that the structures may include an arbitrarynumber of cavities.

[0076] In FIG. 7a is illustrated a design including a 2×2 matrix ofcavities 19 beneath the area where the inductor is intended to beformed. As the areas between the respective cavities are not fullyremoved the membrane supporting structure 20 is in this case a strong,closely connected frame structure of silicon. In FIG. 7a also theplurality of through holes 15 are indicated.

[0077] In FIG. 7b is illustrated a modified version with a plurality ofsmaller cavities 41 between the larger cavities 19. In such manner thesilicon removal area-utilization factor is slightly larger, whereas themechanical strength of the support structure 20 is slightlydeteriorated. In the illustrated case, the larger cavities 19 and thesmaller cavities 41 are overlapping and thus a reduced numeral of verylarge and extended cavities are obtained separated from each other bymeans of the supporting structure 20, which in this instance takes theform of a linearly extending support wall.

[0078] Moreover, the utilization factor can be further increased byarranging the cavities 19 and 41 such that the supporting structure isdivided into a plurality of supporting pillars, of which one 20 is shownin FIG. 7c. The support structure may be strengthen by means of reducingthe number of through holes for the fabrication of the smaller cavities41. Thus, by not forming through holes in e.g. area 43 a further supportmay be left underneath such area.

[0079] Finally, FIG. 7d illustrates a design incorporating a lineararray of cavities 19 and 41. Such design may be used underneath atransmission line or other linearly extended electrical device to reducethe electrical coupling between the line/device and the substrate. InFIG. 7d a plurality of semiconductor substrate pillars 20 are left tosupport the structure. In other versions such pillars may be abundant.

[0080] It shall be appreciated that the present invention is usable fordecreasing the electrical coupling between the substrate and virtuallyany kind of electrical device.

[0081] It shall further be appreciated that the cavities 41 of FIGS.7a-d may be formed and subsequently covered in the same way as cavities19 are formed and covered.

[0082] It shall yet further be appreciated that the embodiments of FIG.7a-d may be modified to achieve virtually any pattern of cavities andsupports. Preferably though, a design is selected which has a goodsilicon removal area-utilization factor and still provides for goodmechanical support for the membrane(s) formed above the cavity/supportstructure.

[0083] Advantages of the Present Invention

[0084] The proposed method increases the isolation gap to the substrateand hence reduces electric losses to the substrate of integratedinductor structures. The quality factor and self-resonance frequency areconsequently improved.

[0085] The method can easily be implemented in an IC-manufacturingprocess flow, with only a few additional steps, using existingmanufacturing technology.

[0086] The residual silicon substrate supports 20 (see FIGS. 3e and 5)provides for a mechanically strong structure, where still a siliconremoval area-utilization factor of more than 90% is obtained, i.e. morethan 90% of the silicon substrate material beneath the inductor isremoved and replaced by air, which has a very low dielectric constant.

[0087] Further Aspects of the Present Invention

[0088] According a further aspect of the present invention a measurementmethod is provided, the method being used to measure the depth of anisotropic silicon etch non-destructively. Such distance is usually notpossible to measure without a destructive test.

[0089] The depth D can be estimated by non-destructive opticalinspection and measurements of the distance X1 from the outermost holeto the edge of cavity 19, see FIG. 3c. Distance X1 is easily observedthrough membrane 24, or by measuring the total width X2 of the cavity(where the width X3 of the matrix of holes 15 is known) . If the ratiobetween the etch rate in horizontal and vertical direction is known(which can be calibrated for a set of etching conditions using SEMcross-section analysis), the etch depth can be directly calculated bymeasuring the etched width of the cavity.

[0090] It will be obvious that the invention may be varied in aplurality of ways. Such variations are not to be regarded as a departurefrom the scope of the invention. All such modifications as would beobvious to one skilled in the art are intended to be included within thescope of the appended claims.

1. In the fabrication of an integrated circuit, particularly anintegrated circuit for radio frequency applications, a method forforming an electrical device structure comprised in said circuit, themethod comprising: providing a semiconductor substrate; forming a firstdielectric layer above said substrate; forming a plurality of throughholes in said first dielectric layer; removing semiconductor substratematerial under the first dielectric layer by means of isotropic etchingusing said first dielectric layer provided with through holes ashardmask, thus forming at least a first cavity in the semiconductorsubstrate underneath said plurality of through holes; forming a seconddielectric layer on top of said first dielectric layer to plug saidplurality of through holes, thereby creating a membrane above said firstcavity; and creating an electrical device above said membrane.
 2. Themethod as claimed in claim 1 wherein said semiconductor substrate is ofsilicon.
 3. The method as claimed in claim 1 wherein said firstdielectric layer is a low-temperature oxide, particularly a PETEOS. 4.The method as claimed in claim 1 wherein said first dielectric layer isplanarized.
 5. The method as claimed in claim 1 wherein said pluralityof through holes are formed by means of lithographic patterning followedby etching, particularly dry-etching such as RIE.
 6. The method asclaimed in claim 1 wherein the plurality of through holes have adiameter of less than 5 μm, preferably less than 1 μm, more preferablyless than 0.5 μm, and most preferably in the range of 0.1-0.2 μm, tofacilitate said subsequent plugging.
 7. The method as claimed in claim 1wherein the distance between adjacent through holes is small enough toensure that the bottom surface of the cavity formed beneath the throughholes is substantially uniform.
 8. The method as claimed in claim 7wherein the distance between adjacent through holes is less than 10 μm,preferably less than 5 μm, more preferably less than 3 μm, and mostpreferably around or slightly less than 1 μm.
 9. The method as claimedin claim 1 wherein the semiconductor substrate material under the firstdielectric layer is removed to a depth of at least 5 μm, preferably ofat least 10 μm, more preferably of at least 15 μm, and most preferablyof approximately 25-30 μm.
 10. The method as claimed in claim 1 whereinsemiconductor substrate material is removed in an area of at least 90%of the total semiconductor substrate area above which the electricaldevice is formed.
 11. The method as claimed in claim 1 wherein thesecond dielectric layer is formed by depositing a three-layer structureof oxide.
 12. The method as claimed in claim 1 wherein the first andsecond dielectric layers are deposited to such thicknesses that theirremaining combined thickness coincides with a suitable device-to-metalisolation thickness.
 13. The method as claimed in claim 1 wherein theelectrical device is an inductor.
 14. The method as claimed in claim 13wherein the inductor is created above said membrane in a multi-layermetallization process comprising the formation of at least two metalliclayers, and the formation of a passivation layer between the metalliclayers, said passivation layer being provided with a via contact hole.15. The method as claimed in claim 1 wherein the electrical device is atransmission conductor.
 16. The method as claimed in claim 1 wherein:said through holes are dividable into a first and a second sub-group,respectively, wherein adjacent through holes within a sub-group are moreclosely located than adjacent through holes belonging to differentsub-groups; semiconductor substrate material is removed under the firstdielectric layer to form a second cavity in the semiconductor substrateunderneath said plurality of through holes, said first and secondcavities being separated by a portion of semiconductor substratematerial; and said second dielectric layer formed on top of said firstdielectric layer to plug said plurality of through holes is supported atleast by said portion of semiconductor substrate material.
 17. Themethod as claimed in claim 16 wherein the distance between adjacentthrough holes belonging to different sub-groups of through holes islarge enough to ensure that said portion of semiconductor substrateseparating the cavities formed beneath said different sub-groups iscapable of supporting said membrane mechanically and hindering the samefrom collapsing.
 18. The method as claimed in claim 17 wherein thedistance between adjacent through holes belonging to differentsub-groups of through holes is selected such that said portion ofsemiconductor substrate separating the cavities formed beneath saiddifferent sub-groups has a width of at least about 1 μm, preferably atleast about 5 μm, more preferably at least about 10 μm, and mostpreferably between about 10 and 20 μm.
 19. The method as claimed inclaim 16 wherein further through holes between said first and secondsub-groups of through holes are formed in said first dielectric layer;and wherein semiconductor substrate material is removed under saidfurther through holes, thus forming at least one passage between said atleast first and second cavities.
 20. The method as claimed in claim 16wherein the number of sub-groups of through holes formed and the numberof cavities formed beneath a single electrical device is at least 4,preferably at least 8, more preferably at least 12, and most preferablybetween 10 and
 20. 21. The method as claimed in claim 19 wherein thenumber of sub-groups of through holes formed and the number of cavitiesformed beneath a single electrical device is at least 4, preferably atleast 8, more preferably at least 12, and most preferably between 10 and20, and wherein said number of cavities and said at least one passageare formed such that said membrane above said number of cavities andsaid at least one passage is supported by semiconductor substratematerial in the form of strings, walls, nets, pillars, or a framework.22. An electrical device structure, particularly an inductor structurefor radio frequency (RF) applications, integrated in an integratedcircuit (IC), wherein said electrical device structure is fabricated byusing the method as claimed in claim
 1. 23. An integrated circuit,particularly an integrated circuit for radio frequency applications,wherein said integrated circuit comprises an electrical device structureas claimed in claim
 22. 24. An electrical device structure, particularlyan inductor structure for radio frequency (RF) applications, integratedin an integrated circuit (IC), said electrical device structurecomprising: a semiconductor substrate; a dielectric layer structurethereon; an electrical device on top of said dielectric layer structure;and a cavity structure in said semiconductor substrate, the upperboundary of which being defined by said dielectric layer structure, andsaid cavity structure having a lateral extension comparable to that ofthe electrical device, and being arranged underneath the electricaldevice to decrease the electrical coupling between the electrical deviceand the substrate, wherein said cavity structure comprises at least oneair-filled space; and said dielectric layer structure includes aplurality of through holes, said through holes being plugged bydielectric material.
 25. The electrical device structure as claimed inclaim 24 wherein said cavity structure comprises a plurality ofair-filled spaces and at least one portion of semiconductor substratematerial extending to the dielectric layer structure for supporting thedielectric layer structure mechanically, said portion of semiconductorsubstrate material separating at least two of said plurality ofair-filled spaces.
 26. The electrical device structure as claimed inclaim 25 wherein said semiconductor substrate is of silicon.
 27. Theelectrical device structure as claimed in claim 25 wherein said portionof semiconductor substrate separating said at least two of saidplurality of air-filled spaces has a width of at least about 1 μm,preferably at least about 5 μm, more preferably at least about 10 μm,and most preferably between about 10 and 20 μm.
 28. The electricaldevice structure as claimed in claim 25 wherein the plurality ofair-filled spaces have a height, i.e. distance from their bottom to thedielectric layer structure, of at least 5 μm, preferably of at least 10μm, more preferably of at least 15 μm, and most preferably ofapproximately 25-30 μm.
 29. The electrical device structure as claimedin claim 25 wherein the plurality of air-filled spaces have an area ofat least 90% of the total semiconductor substrate area above which theelectrical device is formed.
 30. The electrical device structure asclaimed in claim 25 wherein at least two of the plurality of air-filledspaces are communicating with each other by means of an air-filledpassage.
 31. The electrical device structure as claimed in claim 25wherein the number of air-filled spaces underneath a single electricaldevice is at least 4, preferably at least 8, more preferably at least12, and most preferably between 10 and
 20. 32. The electrical devicestructure as claimed in claim 25 wherein said portion of semiconductorsubstrate material separating said at least two of said plurality ofair-filled spaces is a string, a wall, a pillar, or a framework.
 33. Anintegrated circuit, particularly an integrated circuit for radiofrequency applications, wherein said integrated circuit comprises theelectrical device structure as claimed in claim
 24. 34. A method ofetching and measuring etched depth non-destructively, comprising:providing a semiconductor substrate; forming a dielectric layer abovesaid substrate; forming a plurality of through holes in said dielectriclayer; removing semiconductor substrate material under the dielectriclayer by means of isotropic etching using said dielectric layer providedwith through holes as hardmask, thus forming a cavity in thesemiconductor substrate; providing the ratio between the etch rate ofsaid isotropic etching in said semiconductor substrate material in ahorizontal and in a vertical direction, respectively; optically andnon-destructively measuring the horizontal distance from an outermostone of said through holes to an edge of said cavity through saiddielectric layer; and estimating the etched depth, i.e. the etcheddistance in said vertical direction, from said provided etch ratio andsaid measured horizontal distance.